The development of mobile land communications has seen DS-CDMA gain importance in wideband mobile communications and Local Area Networks (LAN) because it is adequate for multimedia communications due to its changeable transmission speed. DS-CDMA performs primary and secondary modulations to modulate information into narrowband, and to spread the spectrum into wideband by spread codes, respectively.
In one type of DS-CDMA communication system, data to be transmitted is modulated in both primary and secondary modulations in the manner of Quadrature Phase-Shift Keying (QPSK). Two different spread code sequences are defined for in-phase and quadrature components of a carrier wave, and the data to be transmitted is divided into the in-phase and quadrature components. This is expressed by complex vectors in formulas (1) and (2), in which I is an information vector and C is a spread-code vector: EQU I=I.sub.i+j.multidot.I.sub.q (1) EQU C=C.sub.i+j.multidot.C.sub.q (2)
Here, Ii is an in-phase component, and Iq is a quadrature-phase component of the information I.
In the primary QPSK modulation, the carrier wave is modulated by Ii into in-phase components of the carrier wave by Ii, and it modulates the carrier wave into quadrature components by Iq. In the secondary QPSK modulation, a spread transmission signals is generated by spreading modulation using spread-code C, as shown in formulas (3) and (4): EQU S.sub.i=I.sub.i.multidot.C.sub.i-I.sub.q.multidot.C.sub.q (3) EQU S.sub.q=I.sub.i.multidot.C.sub.q=I.sub.q.multidot.C.sub.i (4)
When the noise on the transmission route is ignored, a signal R to be received at the receiver side is equal to S which is shown in formulas (5) and (6): EQU R.sub.i=I.sub.i.multidot.C.sub.i-I.sub.q.multidot.C.sub.q (5) EQU R.sub.q=I.sub.i.multidot.C.sub.q+I.sub.q.multidot.C.sub.i (6)
The receiving system performs despreading using complex conjugate code vector (Ci-j.multidot.Cq) of C on transmission. The received signal after despreading is shown in formula (7), using (5) and (6): EQU D=Di+i.multidot.Dq=(Ri+j.multidot.Rq).multidot.(Ci-j.multidot.Cq)=(Ri.multi dot.Ci+Rq.multidot.Cq)+j.multidot.(-Ri.multidot.Cq+Rq.multidot.Ci) (7)
When Ci=Cq in the formula above, the secondary modulation is Binary Phase-Shift Keying (BPSK). In this case, the received signal in the receiving system after despreading is expressed in formula (8), as derived from (7): EQU D=Di+i.multidot.Dq=(Ri.multidot.Ci+Rq.multidot.Ci)+j(-Ri.multidot.Ci+Rq.mul tidot.Ci) (8)
It is proposed for a DS-CDMA mobile and personal communication system that data is modulated by QPSK in both primary and secondary modulations on the upward transmission line from a mobile station to the base station, and by QPSK in the primary modulation and BPSK in the secondary modulation on the downward transmission line from base to mobile station. The secondary modulation of QPSK in the downward line makes the transmission tough against distortion caused by a power amplifier in the transmitter. However, the processing in the receiving system becomes complicated.
FIG. 5 shows a block diagram the conventional complex despreading system for the DS-CDMA system above. A complex matched filter, designated by reference numbers 10 and 11, is used for despreading received signals which is modulated by the primary modulation of QPSK and by the secondary modulation of BPSK. In FIG. 5, the conventional despreading system includes a distributor 1, multiplication circuits 2 and 3, a carrier wave generator 4, a .pi./2 phase shifter 5, Low-Pass Filters (LDP) 6 and 7, adders 8 and 9, an I-channel multiplication and addition circuit 10, a Q-channel multiplication and addition circuit 11, and a spread-code register 12.
A received signal is distributed into two lines by the distributor 1 and quadrically detected by the multiplication circuit 2 and 3. The signal on the first line is multiplied by a carrier wave from the carrier wave generator 4 in the multiplication circuit 2, then the carrier wave is deleted from the multiplication result through the low-pass filter 6. The signal on the second line is multiplied at multiplication circuit 3 by a carrier wave shifted by .pi./2 in phase by the phase shifter 5, then the carrier wave is deleted from the multiplication result through the low-pass filter 7. Therefore, the received signal is quadrically demodulated into a baseband signals on the two lines. The baseband signals Ri and Rq are input to the complex matched filter including consisting of multiplication and addition circuits 10 and 11. To simplify the description, the intermediate frequency amplifying stage is neglected.
The circuits 10 and 11 are matched filters for I-channel and Q-channel, to each of which the in-phase component of spread-code Ci is input from the spread-code register 12. The circuits multiply Ri and Rq by Ci, respectively, and calculate the total sum of the multiplication products, respectively so as to despread the signal on the two lines. These are correlation calculations of Ri.multidot.Ci and Rq.multidot.Cq, respectively. The adders 8 and 9 output the correlation value of Di=Ri.multidot.Ci+Rq.multidot.Ci and Dq=-Ri.multidot.Ci+Rq.multidot.Ci defined in the formula (8), respectively.
Then, the despread corresponding to the secondary modulation of BPSK is completed. So, the in-phase component Di and the quadrature component Dq of the received signal are obtained corresponding to Ii and Iq. According to Di and Dq, Ii and Iq can be reproduced. It will be understood that a complex despread is performed by the system consisting of circuits 8, 9, 10 and 11.
FIG. 6 is an exemplary block diagram of the I- and Q-channel multiplication and addition circuit in FIG. 5. In FIG. 6 components, 51a to 51f are sampling and holding circuits, 52 is a controller, component 53a to 53f are multiplication circuits, component 54 is a reference voltage generator, component 55 is a spread-code register, and components 56 to 61 are adders.
Although the circuit in FIG. 6 has six-chip spread-code sequences and six-steps delay stages for easy understanding, the actual spread-code sequence is much longer than this, and the necessary processing stages have to be set according to the length of the spread-code sequence. This multiplication and addition circuit is a matched filter circuit with small size and low power consumption.
In FIG. 6, the received baseband signal corresponds to Ri or Rq in FIG. 5. This signal is successively distributed to each of the sampling and holding circuits 51a to 51f by the controller 52 for controlling a sampling timing of the sampling and holding circuits 51a to 51f. The output from each of the sampling and holding circuits 51a to 51f is multiplied by the spread-code supplied from the spread-code register 55 in the multiplication circuits 53a to 53f, respectively. The outputs of the multiplication circuits are classified into four groups and the outputs of the groups are added together in the adders 56 to 59, respectively. A correlation value is finally obtained by adding the addition result of the adders 56 to 59 by the adders 60 and 61. A reference voltage Vr is input from the reference voltage generator to the multiplication circuits 53a to 53f for a voltage reference of the multiplication calculations, as described below.
Sampling and holding circuits 51a to 51f use analog computation circuits, which include analog switches, input capacitances, inverting amplifiers, and so on. The inverting amplifiers are structured by serially connecting CMOS inverters in three stages, with feedback capacitances (not shown) between their input and output terminals.
The inverting amplifiers works in the liner transition area of input-output performance of the CMOS inverters. As shown in the block of the sampling and holding circuit 51a, each of the sampling and holding circuits has an analog input switch, an input capacitance and an inverting amplifier. Upon opening the input switch, the baseband signal voltage received is held by the circuit 51a. The input capacitance is equal in the capacity to the capacity of the feedback capacitance. When the input of the inverting amplifier connected to the input capacitance and the feedback capacitance is at a voltage equal to the reference voltage Vr of a value of a half of the supply voltage, the held voltage is output with reversed polarity referencing the reference voltage Vr.
Controller 52 controls the analog input switch in each sampling and holding circuit 51a to 51f so as to once close the total input switches and then to successively open the input switches at the timing corresponding to each chip of the spread code. Thus, the received signal of one symbol period is always held in the sampling holding circuits 51a to 51f, and the held signal is output with reversed polarity referencing to Vr.
As shown in the block of the multiplication circuit 53a, each of the multiplication circuits 53a to 53f has two multiplexer circuits MUX1 and MUX2 with the same configuration. In MUX1 and MUX2, only one transmission gate is conductive when the control signal is high-level, and the other transmission gate is conductive when it is low-level. The first and second input terminals of MUX1 in 53a receive the output voltage from 51a and the reference voltage Vr from 54, respectively. The first and second input terminals of MUX2 in 53a receive the voltage contrary to those of MUX1: the first one receives Vr and the second receives the output voltage of 51a.
The control signals of MUX1 and MUX2 are code data of the chip corresponding to 53a among the spread-code sequence supplied from the spread-code register 55. The outputs from MUX1 and MUX2 are the H-output and L-output of the multiplication circuit 53a, respectively. When the chip value corresponding to the spread code as a control signal is "1", MUX1 outputs the input voltage from 51a and MUX2 outputs Vr. When it is 0, MUX1 outputs Vr and MUX2 outputs the input voltage from 51a.
If Vr is a half of the supply voltage, both H-outputs and L-outputs in 53a to 53f output Vr when the baseband receiving signal is 0.
The H-outputs in 53a to 53c are input to an adder 56, which includes an inverting amplifier connected to three input capacitances. The inverting amplifier is similar to that in 51a to 51f, but the input capacitance is 1/3 of the feedback capacitance and therefore, it outputs 1/3 of the output voltage sum of 53a to 53c. The H-outputs of 53d to 53f are input to an adder 58 which outputs 1/3 of the total sum of the output voltages of 53d to 53f, similar to the adder 56.
The outputs of the adders 56 and 58 are input to an adder 60, both of whose capacitance values are a half of the feedback capacitance: The adder 60 outputs a half of the total sum of the output voltages of 56 and 58. The L-outputs of 53a to 53c are input to 57, which outputs 1/3 of the total sum of the output voltages of 53a to 53c. The L-outputs of 53d to 53f are input to an adder 59, which outputs 1/3 of the total sum of output voltages of 53d to 53f.
The outputs of the adders 60, 57 and 59 are input to an adder 61 which has an input capacitance connected to the adder 60 of a capacity equal to the capacity of a feedback capacitance of the inverting amplifier. The adder 57 and 59 have input capacitances of capacities equal to a half of the capacity of the feedback capacitances. The adder 61 outputs a voltage corresponding to the total sum of the output of the adder 60, a half of the outputs of the adders 57 and 59. This means that the adder 61 generates the difference of two sums: the sum of the outputs from the sampling and holding circuit 51 (51a to 51f) which are connected to the multiplication circuit 53 (53a to 53f) and are supplied the spread-code "1" from the register 55. The sum of the outputs from the sampling and holding circuit 51 which are connected to the multiplication circuit 53 and supplied a spread-code "0". That is, the output voltage is the correlation value of the baseband received signal with the spread-code sequence.
After one-cycle correlation values are output from the adder 61, the sampling and holding circuit which has stored the oldest baseband received signal receives the signal newly input at the next timing of the baseband received signal. Simultaneously, the register 55 shifts the held spread-code sequence by one code and outputs the spread-code sequence. The correlation value between the baseband received signal at the next timing and the spread-code sequence at the same timing is obtained by the similar processing above. Since the held baseband received signal is not transferred by shifting the spread-code in the register, the transfer error of the baseband signal is prevented.
The receiving system shown in FIG. 5 has a pair of matched filters shown in FIG. 6 which includes a plurality of adders 56 to 61, and further the receiving system includes a pair of adders 8 and 9. Therefore, the total circuit is rather complicated and difficult in the circuit arrangement in an integrated circuit (IC).
FIG. 8 shows a block diagram of the second example of the conventional complex despreading system. There are provided an I-channel multiplication and addition circuit 21 and a Q-channel multiplication and addition circuit 22 similar to the circuits 10 and 11 in FIG. 5. Adders 8 and 81 are connected to the circuit 21, and adders 9 and 82 are connected to the circuits 22. The quadrature demodulator in FIG. 5 is not shown for easy understanding. The matched filters 21 and 22 are changeable in tap numbers, that is, spreading ratio. Each of the matched filters 21 and 22 has a N tap output and a (N/2) tap outputs. A spread-code register 12 similar to the register 12 in FIG. 5 outputs spread-code sequence for N chip correlation or (N/2) chip correlation. Due to increased output tap terminals in parallel for changeable spreading ratio, the necessary pairs of adders increase. It results difficulty not only in the circuit arrangement in the matched filter output area, but also in the circuit size. Especially in a large-scale integrated circuit (LSI) for a DS-CDMA mobile and personal communication system employs, it is a serious problem that the complex despreading system above is large in circuit size.
FIG. 9 shows another conventional complex despreading system for over-sampling using matched filters 31, 32, 33 and 34. It alternately samples received signals Ri and Rq in a half-cycle of a spread-code chip (double-sampling). The sampling is performed using two clocks Clk1 and Clk2 having each other's reversed phases and the results are output in parallel. The output results of 31 and 32, and 33 and 34 are usually composed; however, each clock sometimes outputs individually, which requires two pairs of adders 8 and 9 and 81 and 82. Other components of the system are similar to those in FIG. 8, so descriptions therefor is omitted. The matched filters 31 and 32 are for I-channel, and 33 and 34 are for Q-channel. Such over-sampling system needs more circuit size and difficulty in the circuit arrangement.
FIG. 10 (a) shows a complex despreading system using a plurality of sliding correlators as shown in FIG. 10 (b). In FIGS. 10 (a) and 10 (b), 41 to 43 are correlators, 44 is a RAKE combination and demodulation means, 45 and 46 are multiplication circuits, 47 and 48 are integrators, and 91 and 92 are adders. This complex despreading system receives multipath signals by a plurality of sliding correlators instead of one matched filter.
In the selection of matched filters, the system receives multipath signals by only one complex matched filter because spatial integration is performed during one symbol cycle. And in the selection of sliding-correlators, 41 to 43 are necessary in response to the multipath to receive multipath signal because the computation is performed in time order.
In FIG. 10 (a), the in-phase and quadrature components Ri and Rq of received signals are input to 41 to 43, which receive signal sequence of spread code Ci having a predetermined number of chips in one symbol from a spread-code register not shown. Here, setting tracing loops in 41 to 43 makes it possible to receive signal sequences of spread-code Ci(1) to Ci(n) which are controlled to have the chip phase correspond to the time delay of a plurality of waves. As shown in FIG. 10(b), the sliding correlator 41 includes multipliers 45 and 46 for despreading the received signals Ri and Rq by multiplying the signals by a spread-code sequence Ci(n) and by integrating the multiplication results during one symbol cycle by integrators 47 and 48. The despread output from 41 undergoes addition and subtraction in adders 91 and 92 as shown in FIG. 10 (a), then the received signals are output as D(n)=Di(n)+i.multidot.Dq(n). The other correlators 42 to 4n work similarly to the correlator 41. The results of addition and subtraction are input to a rake-combiner & demodulator 44. In 44, the received signals are appropriately weighed and added in-phase, and the received signal is output by reducing multipath reflection.